Analogue-to-digital converter

ABSTRACT

The present invention relates to an analogue-to-digital converter whose output is a cyclic series of pulses, the pulse count of each cycle being proportional to an analogue input signal. The invention is useful, for example, in stage and studio lighting control systems, where the output pulses are used to control the fading of lamps and the occurrence of a burst of pulses may produce a visible step in the brightness of the lamps and it is therefore desirable for the pulses to be distributed over the cycles of the digital output.

United States Patent Anthony Leonard lsaacs lnventor Appl. No.

Filed Patented Assignee Priority London, England 677,217

Oct. 23, 1967 Nov. 30, 1971 Thorn Electronics Lirnite London, EnglandOct. 2 l, 1966 Great Britain 47,339/66 ANALOGUE-TO-DIGITAL CONVERTER 3Claims, 4 Drawing Figs.

U.S. Cl Int. Cl Field of Search References Cited UNITED STATES PATENTS2/1956 Langev in et al.

...340/347 AD 03k 13/02 340/347 2,965,891 12/1960 Martin 340/3473,264,637 8/1966 Parkinson... 340/347 3,296,612 l/l967 Tomozawa 340/3473,239,833 3/1966 Gray 340/347 3,358,281 l2/l967 Masel 340/347 PrimaryExaminer-Maynard R. Wilbur Assistant ExaminerCharles D. MillerArtorneys- Laurence Burns and Norman J. O'Malley I4 [7 CORE CORE DRIVERS970/25 BUFFER STORE O a 400 V RA ISE/ 31 001W D/M UNIT SCA/l/A/ER j .25l/.C.0 D/MMER 20 D I ES R V 23- -24 J l 13 i 0 CHANNEL INPUT D MMERSSEL. SCANNER 22 l 8 PATENTfinuuvaolsn 3,624,539

SHEET 1 BF 3 l4 l7 1 MASTER CORE. CORE w 050. DRIVERS sro/u:

BUFFER N78 STORE I 1 J6 D/A RAISE/ cow. DIM u/v/r 19 g 29 29 22- O/P ISCA/V/VER DIMMER 14 20 CHANNEL uvpur DWMERS 5 SCANNER 22 1 ill -0 0i 9T0 LAMPS BYW ATTORNEY PATENTEU NUVSO |97| sum a nr 3' F 1'54. 3 5 29 rFR M mien-w" Jj V-C-O I6 {V IBIS TABLE ANTHONY LEONARD ISAACS mvemonANALOGUE-TO-DIGITAL CONVERTER According to the present invention thereis provided an analogueto-digital converter comprising a discrete-levelgenerator for providing a cyclic series of discrete signals ofdifferingconstant magnitudes, in which signals whose magnitudes are similar areseparated in time over the period of the cycle of the series of discretesignals, and a comparator for comparing the magnitudes of the discretesignals with an analogue input signal to be converted to a digitalsignal, the comparator either providing output pulses only when adiscrete signal is greater than the analogue signal, or when a discretesignal is less than the analogue signal, whereby cycles of pulses whosecount depends on the analogue signal are pro vided at the comparatoroutput.

The magnitudes of the discrete signals in each cycle are preferably alldifferent, and may bear a logarithmic relationship to one another.

The discrete-level generator may comprise a counter coupled to a pulseoscillator, the counter having a number of binary stages, and each stagehaving a corresponding resistor which is coupled to an electrical sourceand the generator output when that stage is in that one of its stateswhich represents a binary 'one'. The currents appearing at the generatoroutput thus depend on the number counted. A load resistor may of coursebe used to provide a voltage output. The resistors are preferablyarranged with the most significant counter stage coupled to the highestvalued resistor, the next most significant counter stage coupled to thenext highest valued resistor, and so on. This arrangement providesoutput voltages which change as the count changes through all thepossible output voltages but in a sequence which does not depend on themagnitude of the signals.

The analogue signals may be applied to the digital to analogue convertercyclically in a series of time-divided channels. In this case eachdiscrete signal lasts while a complete cycle of channels takes place.The digital output signal for each channel then appears in thesuccessive periods allotted to that channel, and the count for eachanalogue signal is complete when a cycle of discrete signals has beencompleted.

An embodiment of the invention will now be described by way of examplewith reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a stage lighting system including ananalogue to digital converter according to the invention,

FIG. 2 is a part block diagram, part circuit diagram of an analogue todigital converter according to the invention,

FIG. 3 is a table showing the sequence of output pulses from theanalogue to digital converter of FIG. 2, and

FIG. 4 is a part of FIG. 1 modified for variable lamp fading control.

In the stage lighting system of FIG. 1 a bank of dimmers controls groupsof lamps (not shown). The intensity of light from any group of lamps canbe changed by moving the control lever, or dolly, of one of 10 fadersnumbered 0 to 9, two of which, 8 and 9, are shown in FIG. 1. If a dollyis moved in one direction the brightness of a group of lamps selected bya channel selector 13 is continuously increased, at a rate depending onthe position of the dolly, until the lamps are at maximum intensity.Movement of the dolly in the other direction dims the lamp continuously.

Each group of lamps is allocated a channel and eight cores in a corestore 14. One of the cores registers a one-bit on-ofi" signal, and theother seven register a seven-bit brightness count giving the requiredbrightness for the group of lamps. The channels are time divided and forthis purpose a 40 kc./s. master oscillator 15 supplies pulses to adivider circuit 16, having two cascaded divide-byl 0 stages and twocascaded divide-bytwo stages. The first divide by 10 stage gives a unitsoutput, the second divide by 10 stage gives a tens output, and the twodivide-by-two stages give a four state hundreds output. The channels arenumbered from 0 to 399 and have a duration of microseconds. The outputsfrom the divider circuit are passed to core drivers 17, which at thebeginning of each 25 microsecond channel period, using the conventionalhalf current pulses applied to X and Y-axis wires of the matrix of thestore 14, select the eight cores allocated to one of the channels andtransfer their contents to a buffer store 18. The contents of the bufferstore is then converted to an analogue voltage by a digital.to analogueconverter 19. The resultant voltage is passed to a selected dimmer driveunit 20, by an output scanner 2] comprising a sampling matrix of ANDgates controlled by the outputs of the divider circuit 16 feeding 400reservoir capacitors. The sampling matrix, timed from the main dividerwaveforms, decommutates the 400-channel time sequential signal from thedigital-to-analogue converter 19 into 400 parallel signals on the 400reservoir capacitors. These signals, one per lighting channel, areshaped in the dimmer drive units 20 into signals controlling the 400dimmers, one per lighting channel.

At the end of each 25 microsecond period the contents of the bufferstore are read back into the core store, and the contents of the nexteight cores corresponding to the next channel are read into the bufferstore.

The 10 faders are used to enter the required brightness counts into thestore 14 and to change them as necessary. First a channel is selectedusing the channel selector 13- and an input scanner 22. The 10 faderseach supply an adjustable voltage to the input scanner 22. The channelselector panel has 10, 10's buttons marked 0.l0.20....90 and four 100'sbuttons marked 0. 100, 200 and 300 respectively. There are two registersor stores in the channel selector 13, a 10 state l0s register (stages 0,l0, 20,...80 and and a four-state l00s register (stages 0, 100, 200 and300). If the 200 button is depressed and released the s register is setto its 200 state, lighting a signal lamp within or near the 200 buttonand extinguishing all other l00s signal lamps. This condition issustained until another l00s button is operated. If now the 70 button isdepressed and released the 10s register is set to its 70 state, lightinga signal lamp within or near the 70 button and extinguishing all otherl0s signal lamps. Faders 0 to 9 now operate on channels 270 to 279respectively of the 400 channels available, controlling the lamps inlighting channels 270 to 279. If the 10's button 0 is now depressed the10's register is set to its state 0, 10's button 0 is illuminatedinstead of button 70 and faders 0 to 9 operate on channels 200 to 209respectively. If 100s button 0 is next depressed the 100's register isset to 0, 100's button 0 is illuminated instead of the 200 button andfaders 0 to 9 operate on channels 0 to 9 respectively.

With the channel selector set to 270, the 100s and l0s registers in thechannel selector are compared in an AND gate matrix with thecorresponding counters of the divider circuit 16 to produce an outputpulse from the channel selector when the divider circuit is in states270 to 279. In the input scanner 22 the units outputs of the dividercircuit 16 are applied to an AND-gate matrix with the analogue voltageoutputs of the 10 faders and with the outputs of the channel selector.With the 200 and 70 buttons illuminated, the combined output consists ofsamples from fader 0 to output when the divider is in state 270,"fromfader 1 output when the main divider is in state 271, etc., and fromfader 9 output when the main divider is in state 279.

The output of the input scanner 22 is composed of bursts of sequentialsamples of the analogue voltage inputs from the faders, each taken onceper divider circuit cycle, the samples occurring only in those of the400 available channel periods corresponding to the settings of thechannel selector.

Each fader is lightly biased to its mechanical center, and its operatinglever or dolly is moved in one sense to raise the brightness of thelamps it controls and in the opposite sense to dim them. The inputscanner has a two-wire output 23, and 24, the wire 23 only beingenergized by any faders moved from center-zero in the raise" sense, theother wire 24 only being energized by any faders moved from center-zeroin the dim sense. The sense of fader operation is thus wire encoded, notpolarity encoded. The samples vary in magnitude with the displacementsof the fader controls from center-zero; neither output is energized by acontrol set to center-zero.

A voltage-controlled oscillator (V.C.O.) 25, having the block diagram ofFIG. 2 uses a 128-state counter 26 driven by a 100 c./s. waveform fromthe divider 16 to produce an analogue output voltage having 128 distinctlevels. Each level is sustained for one complete 400-channel cycle ofthe divider circuit 16, so that one complete cycle of 128 analoguevoltage levels lasts 1.28 seconds.

A number of resistors R1 to R7, one for each stage of the counter 26,are coupled to their corresponding stages. As the counter receivespulses the resistors are, in efi'ect, connected to, and disconnectedfrom, a battery (not shown) in dependence on the number of pulsesreceived. Thus the current through a resistor R8 and hence the voltageacross the resistor, varies according to the count, providing the 128discrete levels. A comparator 27 compares these levels with the outputsof the input scanner on wires 23 and 24. If the voltage on either outputlead of the input scanner is greater than that across the resistor R8 ina given channel period, the V.C.O. produces from a 40 kc./sec. inputfrom the master oscillator a pulse in that channel period on theappropriate output lead. Thus with channel 273 selected and fader 3 atits centerzero each output of the input scanner is at (or below) zeroduring channel period 273 of the main divider cycle, that is smallerthan any of the 128 analogue voltage levels from the resistor R8. Nopulse then occurs in channel period 273 from either of the two outputs28 and 29 of the V.C.O. If the dolly of fader 3 is set fully in eitherthe raise or the dim sense, one or other of the channel selector outputswill be greater in channel period 273 than all 128 levels of the V.C.O.counter analogue voltage, and the V.C.O. will produce a pulse at eitherits raise output 28 or its dim output 29 in channel period 273 of everycomplete cycle of the divider circuit 16. If fader No. 3 is set onlymidway, in either sense, one of the input scanner outputs will begreater in channel period 273 than about half of the V.C.O. analoguelevels, and the corresponding V.C.O. output terminal will produce anoutput pulse in channel period 273 of about half of the 128 completecycles of the main divider required to produce a complete cycle of thel28state V.C.O. counter. The raise" and dim outputs of the V.C.O. arethus sequences of pulses occurring in any given channel period at ratesvarying with the displacement of the relevant fader dolly fromcenter-zero. Again the sense of displacement is wire encoded at theV.C.O. output.

The pulse rate in any given channel period determines the rate of.change of brightness of the lamps in the relevant lighting channel. ifthe 128 levels formed a regular staircase" waveform the V.C.O. outputpulses in any channel period would occur in bursts, the individualpulses of a burst being spaced by one cycle of the divider circuit, thatis 10 ms., and the burst period being one complete cycle of the V.C.O.counter, that is 1.28 seconds. Even though individual pulses producebrightness changes which are not in themselves individually discernible,bursts of, say, 10 such pulses at intervals of 1.28 seconds wouldproduce noticeable steps in brightness.

To overcome this difficulty, the least significant counter stage 30 isconnected to the most significant resistor R1, that is the resistorhaving the lowest resistance. Thus the difierence between a conventionalanalogue converter using counter stages and resistors and the counter 26and the resistors R1 to R7 is that the resistor network is transposedwith respect to the counter stages. As the count in the counter 26increases currents are passed through the resistors Rl to R7 in thefollowing sequence:

R1 and R2,

R1 and R3, and so on.

Taking as a simple illustration an eight-state counter, the nonnalarrangement with R1 corresponding to the least significant output wouldresult in a stepwise increase in output 1, 2, 1+2==3, 4, 4+l=5, and soon. When the resistors are reversed so that R1 corresponds to the mostsignificant output the result is a sequence of output levels 4, 2,4+2==6, 1, l+-4=5, l+2=3, 1+2+4=7, 0, i.e. 4, 2, 6, l, 5, 3, 7, 0. Thesame number of levels is produced but their magnitudes change in whatmay be termed a pseudorandom" sequence. As the analogue input to thecomparator 27 increases it will first exceed the level 0 of the state 0of the counter and then the level 1 of state 4, and then the level 2 ofstate 2, etcfThe complete table of the states of the eight-state counterfor which pulses occur at different analogue input values is shown inFIG. 3. As

the analogue input to the comparator 27 increases each new pulse in thecomparators output occurs midway between an existing pair of pulses, butno smaller pulse interval is halved until all greater pulse intervalshave been halved.

When the brightness count of a group of lamps, represented by the statesof the eight cores allocated to that group has been read into the bufferstore 18, a raise/dim unit 31 raises or lowers the count at one unit perpulse received along wires 28 or 29. Thus if, for example, the fadercoupled to channel 270 were in its maximum position, the count stored bythe cores allocated to that channel would be increased by 128 duringevery cycle of the counter 26; if this fader were halfway between itsmaximum and center positions, the count would be increased by 64 duringevery cycle of the counter 26.

The relationship between fader setting and rate of change ofbrightnesscount" may be modified by using a fader having a different relationshipof output voltage to dolly position, or by deriving the 128-level V.C.O.divider analogue voltage from a staircase analogue made nonlinear bysuitable modification of the analogue-deriving network.

As is described in detail in our copending application of the same dateentitled improvements in Lighting Systems" (British application No.47344/66), in one form of lighting system the V.C.O. 25 may receiveanalogue voltage inputs from apparatus controlling the fading of lampsallocated to some or all channels. The rate of fading depends on thedifference between the initial lamp brightness and the required lampbrightness, since the pulse output from the V.C.O. depends on ananalogue voltage dependent on this difference. Hence all fade operationsare completed in the same time.

In order to vary fade times as desired an auxiliary V.C.O. 35 (see FIG.4) may be interposed in the connection between thelOO c./s. output ofdivider l6 and the V.C.O. 25 to control the rate at which pulses aresupplied to the counter 26 of the V.C.O. 25. It is necessary to addlogic to the V.C.O. 25 to ensure that it produces only one output pulseper channel per input pulse from the auxiliary V.C.O. 35. Such logic mayconsist, for example, of a gate 36 controlling 40 kc./sec. inputs 37 and38, from the master oscillator 15 to the V.C.O. 25, the gate beingenabled when a bistable circuit 39 is set at the start of a new cycle ofchannels by the output of the auxiliary V.C.O. 35. The bistable circuitis reset at the end of this cycle of channels by the c./s. output fromthe divider 16. Thus the 40 kc./s. gate is enabled for one cycle ofchannels only following an input pulse to the V.C.O. 25 and thegeneration of a new analogue level.

For a sequence of 128 pulses from the divider 16, each of which formerlychanged the level of the analogue input to the comparator 27 of theV.C.O. 25, the auxiliary V.C.O. 35 supplies to the V.C.O. 25 a lessernumber of pulses determined by a control input. In consequence thecomplete cycle of 128 states of V.C.O. 25 takes a longer time and theoutput frequency in each channel is reduced in the same proportion,namely the division ratio" of the auxiliary V.C.O. 35. This divisionratio may be varied by varying the auxiliary V.C.O. control input togive overall control of fade time. The control input may be set manuallyor may be the analogue output of a channel reserved for such use.

if the auxiliary V.C.O. analogue levels are based on a linear staircasethe fade rates, being directly proportional to the V.C.O. outputfrequency, are proportional to the auxiliary V.C.O.control voltage. Ifthe manual control for this voltage is linear or if a linear voltmeteris used to indicate the control voltage, and hence the selected fadetime either may be calibrated in fade time but scale shapes will becramped at theslow (minimum voltage) end of the control range because ofthe inverse control law. Since fade time varies inversely with auxiliaryV.C.O. output frequency the control law is hyperbolic.

The auxiliary V.C.0. 35 its control voltage is, say,

produces an output pulse whenever greater than the prevailing one of itsor equal to N of differing case, for a control voltage v imum controlvoltage V, v/V=l/L k log n/N=k log f/F or f/F= e'", i.e. the frequencyratio is an exponential function of the control voltage. Fade time isinversely proportional to the auxiliary V.C.O. output frequency, hencethe ratio t/T of actual fade time t to minimum fade time T is given byt/T=F/f=v/kV This gives a "reverse exponential" scale shape to thevoltmeter or the manual control, or a direct exponential scale shapecontrol or indicator having a reading accuracy which is a constantfraction of the fade time set or indicated.

The relationship between the levels of the output signals provided bythe counter 26 and the resistors R1 to R8 is preferably arithmetic inthe V.C.O.25 and logarithmic in the V.C.O.35.

A meter is associated with each fader and is controlled with it by thechannel selector and input and output scanners to indicate thebrightness count in the channel on which the fader tion of the progressof a fade, one indicating fade up progress and the other fade downprogress, since the rates for these may be chosen independently. Since aselected fade time applies to all channels changed in that sense themetering channels may be arranged to count over an arbitrary range andthe meters monitoring the decommutated analogue outputs for thesechannels may be scaled in percent completion" of fade. The meteringcounters are set to their starting states by operation of anyappropriate selector button, e.g. add,"fade."

The V.C.O.25 may be divided into two parts one for raising brightnessand one for dimming brightness. Each part has separate connections tothe divider 16. Two auxiliary V.C.0s may then be connected in theseparate connections to give fast raise, slow dim, or slow raise, fastdim operation. Several auxiliary V.C.Os may be used in each separateconnection to give fixed and variable fade time control.

Very slow rates of change for prolonged "sunrise" set effects may beobtained using auxiliary V.C.O. 's.

I claim:

1. An analogue-to-digital converter comprising:

a. a discrete-level generator generating a cyclic series of discretesignals of differing constant magnitudes, in which signals whosemagnitudes are similar are separated in time over the period of thecycle of the series of discrete signals, said generator comprisin acounter having a number of binary stages,

a group of resistors each corresponding to one of the stages of thecounter,

electrical source means,

a generator output terminal,

means coupling the stages of the counter to the resistors, the mostsignificant counter stage being coupled to the highest valued resistorand the less significant stages being coupled to resistors ofprogressively lower values, whereby when a counter stage is in itsbinary one" state the corresponding resistor is connected between saidelectrical source means and said generator output terminal, and

a pulse oscillator coupled to said counter; and

a comparator coupled to said generator and to the analogue input tocompare the magnitudes of the discrete signals with an analogue inputsignal to be converted to a digital signal,

said comparator being constructed to provide an output pulse only when adiscrete signal is less than, or only when it is greater than, theanalogue signal, whereby cycles of pulses whose count depends on theanalogue signal are provided at the comparator output.

2. A converter as claimed in claim 1 including means for applyinganalogue signals to the converter in a series of time-divided channelsand for controlling the discrete-level generator to maintain eachdiscrete level for a complete cycle of the said channels.

or "sun-

1. An analogue-to-digital converter comprising: a. a discrete-levelgenerator generating a cyclic series of discrete signals of differingconstant magnitudes, in which signals whose magnitudes are similar areseparated in time over the period of the cycle of the series of discretesignals, said generator comprising a counter having a number of binarystages, a group of resistors each corresponding to one of the stages ofthe counter, electrical source means, a generator output terminal, meanscoupling the stages of the counter to the resistors, the mostsignificant counter stage being coupled to the highest valued resistorand the less significant stages being coupled to resistors ofprogressively lower values, whereby when a counter stage is in itsbinary ''''one'''' state the corresponding resistor is connected betweensaid electrical source means and said generator output terminal, and apulse oscillator coupled to said counter; and b. a comparator coupled tosaid generator and to the analogue input to compare the magnitudes ofthe discrete signals with an analogue input signal to be converted to adigital signal, said comparator being constructed to provide an outputpulse only when a discrete signal is less than, or only when it isgreater than, the analogue signal, whereby cycles of pulses whose countdepends on the analogue signal are provided at the comparator output. 2.A converter as claimed in claim 1 including means for applying analoguesignals to the converter in a series of time-divided channels and forcontrolling the discrete-level generator to maintain each discrete levelfor a complete cycle of the said channels.
 3. A converter as claimed inclaim 1 wherein the pulse oscillator is coupled to means for applying agroup of analogue signals to the converter in a series of time-dividedchannels, the duration of each of the discrete levels of the generatorcorresponding to a complete cycle of the said channels.